Move CTest to project root

This commit is contained in:
Mario Romero 2023-02-07 22:33:01 -03:00
parent c83e16a145
commit 96748e6f22
4 changed files with 83 additions and 2 deletions

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@ -1,5 +1,8 @@
cmake_minimum_required(VERSION 3.10) cmake_minimum_required(VERSION 3.10)
project(rvscc) project(rvscc)
set_property(GLOBAL PROPERTY CTEST_TARGETS_ADDED 1)
include(CTest)
include(ExternalProject) include(ExternalProject)
ExternalProject_Add(firmware ExternalProject_Add(firmware

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@ -0,0 +1,14 @@
set(CMAKE_SYSTEM_NAME Generic)
find_program(RISCV_GCC_FOUND
NAMES riscv-none-elf-gcc riscv32-unknown-elf-gcc)
get_filename_component(GCC_BIN ${RISCV_GCC_FOUND} NAME)
string(REPLACE gcc "" TOOLCHAIN_PREFIX ${GCC_BIN})
set(CMAKE_ASM_COMPILER ${TOOLCHAIN_PREFIX}as)
set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}gcc)
set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}g++)
set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}objcopy)
set(CMAKE_OBJDUMP ${TOOLCHAIN_PREFIX}objdump)

66
cmake/utils.cmake Normal file
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@ -0,0 +1,66 @@
cmake_minimum_required(VERSION 3.10)
function(rvscc_bin_to_verilog_mem_file)
cmake_parse_arguments(RVSCC
""
"TARGET"
""
${ARGN}
)
add_custom_command(TARGET ${RVSCC_TARGET} POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -j .text
-O verilog
--verilog-data-width=1
--reverse-bytes=4
"$<TARGET_FILE:${RVSCC_TARGET}>" ${RVSCC_TARGET}.mem
COMMENT "Invoking: Verilog Hexdump"
)
endfunction()
function(rvscc_dissasemble)
cmake_parse_arguments(RVSCC
""
"TARGET"
""
${ARGN}
)
add_custom_command(TARGET ${RVSCC_TARGET} POST_BUILD
COMMAND ${CMAKE_OBJDUMP} -S "$<TARGET_FILE:${RVSCC_TARGET}>" > ${RVSCC_TARGET}.disasm
COMMENT "Invoking: Disassemble"
)
endfunction()
function(rvscc_add_test)
cmake_parse_arguments(TEST
""
"NAME"
"SOURCES"
${ARGN}
)
message("Adding test ${TEST_NAME}")
set(TEST_TARGET_NAME test-${TEST_NAME})
add_executable(${TEST_TARGET_NAME} sim_individual_test.cpp)
if ("${CMAKE_BUILD_TYPE}" EQUAL "Release")
verilate(${TEST_TARGET_NAME}
SOURCES ${TEST_SOURCES}
SYSTEMC
VERILATOR_ARGS --timing
)
else() # Debug
verilate(${TEST_TARGET_NAME}
SOURCES ${TEST_SOURCES}
TRACE
SYSTEMC
VERILATOR_ARGS --timing
)
endif()
set_property(TARGET ${TEST_TARGET_NAME} PROPERTY CXX_STANDARD ${SystemC_CXX_STANDARD})
verilator_link_systemc(${TEST_TARGET_NAME})
list(GET TEST_SOURCES 0 TEST_TOP_MODULE)
get_filename_component(TEST_TOP_MODULE_NAME ${TEST_TOP_MODULE} NAME_WE)
target_compile_definitions(${TEST_TARGET_NAME} PRIVATE
TEST_HEADER="V${TEST_TOP_MODULE_NAME}.h"
TEST_CLASS=V${TEST_TOP_MODULE_NAME}
)
add_test(NAME ${TEST_TARGET_NAME} COMMAND ${TEST_TARGET_NAME})
endfunction()

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@ -2,8 +2,6 @@ cmake_minimum_required(VERSION 3.10)
project(rvscc-tests CXX) project(rvscc-tests CXX)
include(CTest)
find_package(verilator HINTS $ENV{VERILATOR_ROOT}) find_package(verilator HINTS $ENV{VERILATOR_ROOT})
if (NOT verilator_FOUND) if (NOT verilator_FOUND)
message(FATAL_ERROR "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable") message(FATAL_ERROR "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable")