From 7fca64f35e5ff2fb262b83811c1fff854640a308 Mon Sep 17 00:00:00 2001 From: Mario Romero Date: Fri, 2 Dec 2022 21:22:13 -0300 Subject: [PATCH] Describe Register File --- rtl/RegisterFile.sv | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/rtl/RegisterFile.sv b/rtl/RegisterFile.sv index 515530e..2670dd4 100644 --- a/rtl/RegisterFile.sv +++ b/rtl/RegisterFile.sv @@ -3,6 +3,7 @@ // N = Bit width module RegisterFile #( parameter N_REG_ADDR = 5, +parameter N_REG = 32, parameter N_DATA = 32 ) ( input logic clk, @@ -11,4 +12,14 @@ parameter N_DATA = 32 input logic[N_DATA-1:0] write_data_3, output logic[N_DATA-1:0] read_data_1, read_data_2 ); + logic[N_REG:0] mem; + + always_ff @(posedge clk) begin + if (write_enable_3) + mem[addr_3] <= write_data_3; + else begin + read_data_1 <= mem[addr_1]; + read_data_2 <= mem[addr_2]; + end + end endmodule