Fix cache memory test
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03c30636e9
commit
54b3083319
@ -26,17 +26,17 @@ module cache_memory #(
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logic [NUM_WAYS - 1:0] hits;
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logic [NUM_WAYS - 1:0] hits;
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logic [WaySize-1:0] way;
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logic [WaySize-1:0] way;
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logic [WaySize-1:0] read_way;
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logic [WaySize-1:0] read_way;
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priority_encoder #(.N(WaySize)) read_way_encoder (
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priority_encoder #(
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.N(WaySize)
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) read_way_encoder (
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.data_in(hits),
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.data_in(hits),
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.data_out(read_way),
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.data_out(read_way),
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.valid(hit)
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.valid(hit)
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);
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);
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always_comb begin
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always_comb begin
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if(write_enable)
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if (write_enable) way = write_way;
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way = write_way;
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else way = read_way;
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else
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way = read_way;
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end
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end
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typedef struct packed {
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typedef struct packed {
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@ -75,9 +75,11 @@ module cache_memory #(
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end
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end
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end
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end
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priority_encoder #(.N(WaySize)) populate_way_encoder (
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priority_encoder #(
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.N(WaySize)
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) populate_way_encoder (
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.data_in(valid_flags),
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.data_in(valid_flags),
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.data_out(populate_way),
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.data_out(populate_way),
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.valid('dz)
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.valid()
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);
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);
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endmodule
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endmodule
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@ -9,7 +9,7 @@ module priority_encoder #(
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output logic valid
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output logic valid
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);
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);
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always_comb begin
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always_comb begin
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data_out = 3'dx;
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data_out = N'('dx);
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for (int i = 0; i < 2 ** N; i++) begin
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for (int i = 0; i < 2 ** N; i++) begin
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if (data_in[i]) data_out = i[N-1:0];
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if (data_in[i]) data_out = i[N-1:0];
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end
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end
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@ -101,5 +101,6 @@ rvscc_add_test(
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NAME cache-memory
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NAME cache-memory
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TOP test_cache_memory
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TOP test_cache_memory
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SOURCES ${PROJECT_SOURCE_DIR}/rtl/cache_memory.sv
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SOURCES ${PROJECT_SOURCE_DIR}/rtl/cache_memory.sv
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${PROJECT_SOURCE_DIR}/rtl/priority_encoder.sv
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${PROJECT_SOURCE_DIR}/test/test_cache_memory.sv
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${PROJECT_SOURCE_DIR}/test/test_cache_memory.sv
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)
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)
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@ -10,7 +10,7 @@ module test_cache_memory ();
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logic write_enable;
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logic write_enable;
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logic [31:0] write_data;
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logic [31:0] write_data;
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logic [31:0] read_data;
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logic [31:0] read_data;
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logic read_valid;
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logic hit;
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logic [dut.WaySize-1:0] populate_way;
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logic [dut.WaySize-1:0] populate_way;
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cache_memory #(
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cache_memory #(
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.ADDR_SIZE (32),
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.ADDR_SIZE (32),
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@ -26,7 +26,7 @@ module test_cache_memory ();
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.write_enable(write_enable),
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.write_enable(write_enable),
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.write_data(write_data),
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.write_data(write_data),
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.read_data(read_data),
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.read_data(read_data),
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.read_valid(read_valid),
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.hit(hit),
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.populate_way(populate_way)
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.populate_way(populate_way)
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);
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);
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@ -51,12 +51,12 @@ module test_cache_memory ();
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write_enable = 0;
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write_enable = 0;
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tag += 1;
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tag += 1;
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#1;
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#1;
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assert (read_valid == 0)
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assert (hit == 0)
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else $error("Valid flags does not match");
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else $error("Valid flags does not match");
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#ClockCycle;
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#ClockCycle;
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tag -= 1;
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tag -= 1;
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#1;
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#1;
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assert (read_valid == 1)
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assert (hit == 1)
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else $error("Valid flags does not match");
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else $error("Valid flags does not match");
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$finish;
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$finish;
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end
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end
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