Update two way LRU cache

Dockerfile

@@ -1,5 +1,5 @@
 # RVSCC developer enviroment
-FROM alpine
+FROM alpine:edge
 MAINTAINER Mario Romero <mario@1159.cl>
 
 # Install packages

rtl/cache_controller.sv

@@ -10,6 +10,7 @@ module cache_controller #(
     input logic write_enable,
     input logic [$clog2(NUM_WAYS) - 1:0] replace_way,
     input logic [$clog2(NUM_WAYS) - 1:0] populate_way,
+    input logic populated,
     output logic cru_enable,
     output logic [$clog2(NUM_WAYS) - 1:0] write_way,
     output logic [$clog2(NUM_SETS) - 1:0] set,
@@ -22,9 +23,9 @@ module cache_controller #(
   localparam int WaySize = $clog2(NUM_WAYS);
 
   typedef struct packed {
-    logic [ByteOffsetSize - 1:0] byte_offset;
-    logic [SetSize - 1:0] set;
     logic [TagSize - 1:0] tag;
+    logic [SetSize - 1:0] set;
+    logic [ByteOffsetSize - 1:0] byte_offset;
   } cache_addr_t;
 
   typedef enum logic [1:0] {
@@ -36,15 +37,12 @@ module cache_controller #(
   cache_addr_t  packed_addr;
   cache_state_t state;
 
-  logic [WaySize - 1:0]  next_populate_way;
- 
-  logic valid;
   always_comb begin
     packed_addr = cache_addr_t'(addr);
     set = packed_addr.set;
     tag = packed_addr.tag;
 
-    state = cache_state_t'{write_enable, valid};
+    state = cache_state_t'{write_enable, populated};
     case (state)
       READ: begin
         cru_enable = 0;
@@ -52,7 +50,7 @@ module cache_controller #(
       end
       WRITE_POPULATE: begin
         cru_enable = 0;
-        write_way = next_populate_way;
+        write_way = populate_way;
       end
       WRITE_REPLACE: begin
         cru_enable = 1;
@@ -63,6 +61,6 @@ module cache_controller #(
         write_way = 'dx;
       end
     endcase
-    next_populate_way = populate_way + 'd1;
   end
+
 endmodule

rtl/cache_memory.sv

@@ -15,6 +15,7 @@ module cache_memory #(
     input logic [BLOCK_SIZE - 1:0] write_data,
     output logic [BLOCK_SIZE - 1:0] read_data,
     output logic [$clog2(NUM_WAYS) - 1:0] populate_way,
+    output logic populated,
     output logic hit
 );
   localparam int NumBlockBytes = BLOCK_SIZE / 4;
@@ -75,11 +76,28 @@ module cache_memory #(
     end
   end
 
+  logic valid_flags_index_valid;
+  logic[WaySize-1:0] valid_flags_index;
+
   priority_encoder #(
       .N(WaySize)
   ) populate_way_encoder (
       .data_in(valid_flags),
-      .data_out(populate_way),
+      .data_out(valid_flags_index),
-      .valid()
+      .valid(valid_flags_index_valid)
   );
+  /*
+  generate
+    if (WaySize > 1)
+        always_comb populated &= populate_way;
+    else
+        assign populated = populate_way;
+  endgenerate*/
+  
+  always_comb begin
+    if(valid_flags_index_valid)
+        {populated, populate_way} = valid_flags_index + 'd1;
+    else
+        {populated, populate_way} = 'd0;
+  end
 endmodule

rtl/data_memory_if.sv

@@ -11,11 +11,12 @@ interface data_memory_if #(
   logic write_enable;
   logic [DATA_SIZE-1:0] write_data;
   logic [DATA_SIZE-1:0] read_data;
-  logic valid;
+  logic hit;
   logic ready;
 
   modport datapath(input read_data, output addr, write_enable, write_data);
   modport ram(input clk, rst, addr, write_enable, write_data, output read_data);
+  modport cache(input clk, rst, addr, write_enable, write_data, output read_data, hit);
   modport test(input read_data, write_enable, write_data);
 
   /*

rtl/two_way_lru_cache.sv

@@ -5,13 +5,7 @@ module two_way_lru_cache #(
     parameter int NUM_SETS   = 16,
     parameter int BLOCK_SIZE = 32
 ) (
-    input logic clk,
+    data_memory_if.cache data_mem_if
-    input logic rst,
-    input logic [ADDR_SIZE - 1:0] addr,
-    input logic write_enable,
-    input logic [BLOCK_SIZE - 1:0] write_data,
-    output logic [BLOCK_SIZE - 1:0] read_data,
-    output logic hit
 );
   localparam int NumWays = 2;
   localparam int NumBlockBytes = BLOCK_SIZE / 4;
@@ -33,16 +27,17 @@ module two_way_lru_cache #(
       .NUM_WAYS  (NumWays),
       .BLOCK_SIZE(BLOCK_SIZE)
   ) cache_memory (
-      .clk(clk),
+      .clk(data_mem_if.clk),
-      .rst(rst),
+      .rst(data_mem_if.rst),
       .write_way(write_way),
       .set(set),
       .tag(tag),
-      .write_enable(write_enable),
+      .write_enable(data_mem_if.write_enable),
-      .write_data(write_data),
+      .write_data(data_mem_if.write_data),
-      .read_data(read_data),
+      .read_data(data_mem_if.read_data),
       .populate_way(populate_way),
-      .hit(hit)
+      .populated(populated),
+      .hit(data_mem_if.hit)
   );
 
   two_way_lru_cru #(
@@ -50,9 +45,9 @@ module two_way_lru_cache #(
       .NUM_SETS  (NUM_SETS),
       .BLOCK_SIZE(BLOCK_SIZE)
   ) cache_replace_unit (
-      .clk(clk),
+      .clk(data_mem_if.clk),
-      .rst(rst),
+      .rst(data_mem_if.rst),
-      .addr(addr),
+      .addr(data_mem_if.addr),
       .replace(cru_enable),
       .preferred(replace_preferred_way)
   );
@@ -63,10 +58,11 @@ module two_way_lru_cache #(
       .NUM_WAYS  (NumWays),
       .BLOCK_SIZE(BLOCK_SIZE)
   ) cache_controller (
-      .addr(addr),
+      .addr(data_mem_if.addr),
-      .write_enable(write_enable),
+      .write_enable(data_mem_if.write_enable),
       .replace_way(replace_preferred_way),
       .populate_way(populate_way),
+      .populated(populated),
       .cru_enable(cru_enable),
       .write_way(write_way),
       .set(set),

rtl/two_way_lru_cru.sv

@@ -29,7 +29,7 @@ module two_way_lru_cru #(
 
   assign preferred = lru[packed_addr.set];
   always_ff @(posedge clk) begin
-    if (rst) lru[packed_addr.set] <= 0;
+    if (rst) lru <= 'd0;
     else if (replace) begin
       lru[packed_addr.set] <= !lru[packed_addr.set];
     end