13 lines
182 B
Systemverilog
13 lines
182 B
Systemverilog
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`timescale 1ns / 1ps
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module Extend
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#(
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parameter N_IN = 12,
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parameter N_OUT = 32
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) (
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input logic enable,
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input logic[N_IN-1:0] imm,
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output logic[N_OUT-1:0] imm_ext
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);
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endmodule
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