16 lines
262 B
Systemverilog
16 lines
262 B
Systemverilog
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`timescale 1ns / 1ps
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module Test_ALU();
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logic[31:0] a, b;
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logic[2:0] opcode;
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logic[31:0] result;
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logic[3:0] status;
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ALU alu(a, b, opcode, result, status);
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initial begin
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a = 'd3;
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b = 'd11;
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opcode = 'd0;
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end
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endmodule
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