10 lines
158 B
Systemverilog
10 lines
158 B
Systemverilog
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`timescale 1ns / 1ps
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// N = Bit width
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module InstructionMemory #(parameter N = 8)
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(
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input logic[N-1:0] addr,
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output logic[N-1:0] instr
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);
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endmodule
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