18 lines
326 B
Systemverilog
18 lines
326 B
Systemverilog
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`timescale 1ns / 1ps
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module ControlUnit
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(
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input logic[6:0] opcode,
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input logic[2:0] funct_3,
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input logic[6:0] funct_7,
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input logic zero,
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output logic pc_src,
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output logic[1:0] result_src,
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output logic mem_write,
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output logic[2:0] alu_ctrl,
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output logic alu_src,
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output logic[1:0] imm_src,
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output logic reg_write
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);
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endmodule
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