31 lines
467 B
Systemverilog
31 lines
467 B
Systemverilog
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`timescale 1ns / 1ps
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module test_single_cycle_core ();
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logic clk, rst;
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always #1 clk = ~clk;
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single_cycle_datapath dut (
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.clk(clk),
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.rst(rst),
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.mem_if(mem_if.datapath)
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);
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data_memory_if mem_if (
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.clk(clk),
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.rst(rst)
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);
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data_memory mem (.mem_if(mem_if.ram));
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initial begin
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$dumpfile("single_cycle.vcd");
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$dumpvars(1, dut);
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clk = 0;
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rst = 1;
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#4;
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rst = 0;
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#100;
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$finish;
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end
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endmodule
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