30 lines
462 B
Systemverilog
30 lines
462 B
Systemverilog
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`timescale 1ns / 1ps
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module test_cache_memory ();
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logic [31:0] addr, write_data, read_data;
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logic clk, rst, write_enable;
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CacheMemory cache_memory (
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.clk(clk),
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.rst(rst),
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write_enable,
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write_data,
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read_data
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);
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always #5 clk = ~clk;
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initial begin
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clk = 0;
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rst = 1;
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write_enable = 0;
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#25 rst = 0;
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addr = 'd7;
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write_enable = 1;
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write_data = 'd10;
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#25 write_enable = 0;
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end
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endmodule
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