35 lines
779 B
Systemverilog
35 lines
779 B
Systemverilog
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`timescale 1ns / 1ps
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module test_priority_encoder();
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logic [7:0] data_in;
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logic [2:0] data_out;
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logic valid;
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priority_encoder #(
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.N(3)
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) encoder (
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.data_in(data_in),
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.data_out(data_out),
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.valid(valid)
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);
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initial begin
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data_in = 'b00000001;
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for (int i = 0; i < 8; i++) begin
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#1
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assert (data_out == i[2:0] && valid == 1)
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else $error("Failed one-hot to index check at iteration %0d, %d", i, data_out);
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data_in = data_in << 'd1;
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end
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data_in = 'b00101111;
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#1
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assert (data_out == 'd5)
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else $error("Incorrect result with input %b", data_in);
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data_in = 'b10101010;
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#1
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assert (data_out == 'd7)
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else $error("Incorrect result with input %b", data_in);
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$finish;
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end
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endmodule
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