19 lines
468 B
Systemverilog
19 lines
468 B
Systemverilog
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interface data_memory_if #(
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parameter int ADDR_SIZE = 32,
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parameter int DATA_SIZE = 32
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) (
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input logic clk,
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input logic rst
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);
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logic [ADDR_SIZE-1:0] addr;
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logic write_enable;
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logic [DATA_SIZE-1:0] write_data;
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logic [DATA_SIZE-1:0] read_data;
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logic valid;
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logic ready;
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modport datapath(input read_data, output addr, write_enable, write_data);
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modport ram(input clk, rst, addr, write_enable, write_data, output read_data);
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endinterface
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