31 lines
500 B
Systemverilog
31 lines
500 B
Systemverilog
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`timescale 1ns / 1ps
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module Test_DataMemory();
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logic clk;
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logic[31:0] addr;
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logic write_enable;
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logic[31:0] write_data;
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logic[31:0] read_data;
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DataMemory data_memory(
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clk,
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addr,
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write_enable,
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write_data,
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read_data
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);
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always #1 clk = ~clk;
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initial begin
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clk=0;
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addr='d11;
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#5
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write_enable=1;
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#5
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write_data=1;
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#5
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write_enable=0;
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end
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endmodule
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