RVSCC/rtl/ALU.sv

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`timescale 1ns / 1ps
// N = Bit width
module ALU #(parameter N = 32)
(
input logic[N-1:0] a,
input logic[N-1:0] b,
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input logic[2:0] opcode,
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output logic[N-1:0] result,
output logic[3:0] status
);
logic n, z, c, v;
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logic opsign_comp, v_value;
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always_comb begin
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// Check if the signs of the operands are equal considering substraction sign simplification over the B operand
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opsign_comp = (a[N-1] == (b[N-1] ^ opcode[0]));
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// There is an overflow if the signs are equal and the result differ from the operation sign
// The overflow flag only gets assign when the operation is either a sum or a substraction
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v_value = opsign_comp && (result != a[N-1]);
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case(opcode)
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'b000: begin // Addition
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{c, result} = a + b;
v = v_value;
end
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'b001: begin // Substraction
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{c, result} = a - b;
v = v_value;
end
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'b011: begin // Or
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result = a | b;
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c = 'b0;
v = 'b0;
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end
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'b010: begin // And
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result = a & b;
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c = 'b0;
v = 'b0;
end
'b101: begin // Set less than
result = a < b;
c = 'b0;
v = 'b0;
end
default: begin
result = 'dx;
c = 'dx;
v = 'dx;
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end
endcase
n = result[N-1];
z = (result == '0);
status = {n, z, c, v};
end
endmodule