91 lines
2.4 KiB
Systemverilog
91 lines
2.4 KiB
Systemverilog
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`timescale 1ns / 1ps
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module MainDecoder(
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input logic[6:0] opcode,
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output logic branch,
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output logic jump,
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output logic[1:0] result_src,
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output logic mem_write,
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output logic[2:0] alu_ctrl,
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output logic alu_src,
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output logic[1:0] imm_src,
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output logic reg_write,
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output logic[1:0] alu_op
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);
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always_comb begin
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case(opcode)
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'b0000011: begin // lw
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reg_write = 1;
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imm_src = 'b00;
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alu_src = 1;
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mem_write = 0;
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result_src = 'b01;
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branch = 0;
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alu_op = 'b00;
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jump = 0;
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end
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'b0100011: begin // sw
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reg_write = 0;
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imm_src = 'b01;
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alu_src = 1;
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mem_write = 1;
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result_src = 'bxx;
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branch = 0;
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alu_op = 'b00;
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jump = 0;
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end
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'b0110011: begin // r-type
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reg_write = 1;
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imm_src = 'bxx;
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alu_src = 0;
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mem_write = 0;
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result_src = 'b00;
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branch = 0;
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alu_op = 'b10;
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jump = 0;
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end
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'b1100011: begin // beq
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reg_write = 0;
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imm_src = 'b10;
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alu_src = 0;
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mem_write = 0;
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result_src = 'bxx;
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branch = 1;
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alu_op = 'b01;
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jump = 0;
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end
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'b0010011: begin // i-type
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reg_write = 1;
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imm_src = 'b00;
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alu_src = 1;
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mem_write = 0;
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result_src = 'b00;
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branch = 0;
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alu_op = 'b10;
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jump = 0;
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end
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'b1101111: begin // jal
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reg_write = 1;
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imm_src = 'b11;
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alu_src = 'bx;
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mem_write = 0;
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result_src = 'b10;
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branch = 0;
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alu_op = 'bxx;
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jump = 1;
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end
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default: begin
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reg_write = 'bx;
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imm_src = 'bxx;
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alu_src = 'bx;
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mem_write = 'bx;
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result_src = 'bx;
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branch = 'bx;
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alu_op = 'bx;
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jump = 'bx;
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end
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endcase
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end
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endmodule
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