66 lines
1.5 KiB
Systemverilog
66 lines
1.5 KiB
Systemverilog
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`timescale 1ns / 1ps
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module alu_decoder(
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input logic opcode_5,
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input logic [2:0] funct_3,
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input logic funct_7_5,
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input logic [1:0] alu_op,
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output logic [2:0] alu_ctrl,
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output logic branch_neg
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);
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always_comb begin
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casez ({
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alu_op, funct_3, opcode_5, funct_7_5
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})
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'b00?????: begin
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alu_ctrl = 3'b000; // lw sw
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branch_neg = 1'dx;
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end
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'b01000??: begin
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alu_ctrl = 3'b001; // beq
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branch_neg = 1'd1;
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end
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'b01100??: begin
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alu_ctrl = 3'b101; // blt
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branch_neg = 1'd0;
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end
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'b01101??: begin
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alu_ctrl = 3'b101; // bge
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branch_neg = 1'd1;
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end
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'b1000000: begin
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alu_ctrl = 3'b000; // add
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branch_neg = 1'dx;
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end
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'b1000001: begin
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alu_ctrl = 3'b000; // add
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branch_neg = 1'dx;
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end
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'b1000010: begin
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alu_ctrl = 3'b000; // add
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branch_neg = 1'dx;
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end
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'b1000011: begin
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alu_ctrl = 3'b001; // sub
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branch_neg = 1'dx;
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end
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'b10010??: begin
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alu_ctrl = 3'b101; // slt
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branch_neg = 1'dx;
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end
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'b10110??: begin
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alu_ctrl = 3'b000; // or
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branch_neg = 1'dx;
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end
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'b10111??: begin
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alu_ctrl = 3'b000; // and
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branch_neg = 1'dx;
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end
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default: begin
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alu_ctrl = 3'bxxx;
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branch_neg = 1'dx;
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end
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endcase
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end
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endmodule
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