89 lines
2.4 KiB
Systemverilog
89 lines
2.4 KiB
Systemverilog
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`timescale 1ns / 1ps
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module CacheController #(
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parameter ADDR_SIZE = 32,
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parameter NUM_SETS = 16,
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parameter NUM_WAYS = 4,
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parameter BLOCK_SIZE = 32
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) (
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input logic clk,
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input logic[ADDR_SIZE - 1:0] addr,
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input logic write_enable,
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input logic replace_way,
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input logic[NUM_WAYS - 1:0] hits,
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input logic[NUM_WAYS - 1:0] valid_flags,
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output logic[SET_SIZE - 1:0] set,
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output logic[TAG_SIZE - 1:0] tag,
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output logic[WAY_SIZE - 1:0] way,
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output logic hit,
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output logic cru_enable
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);
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localparam NUM_BLOCK_BYTES = BLOCK_SIZE / 4;
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localparam BYTE_OFFSET_SIZE = $clog2(NUM_BLOCK_BYTES);
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localparam SET_SIZE = $clog2(NUM_SETS);
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localparam TAG_SIZE = ADDR_SIZE - SET_SIZE - BYTE_OFFSET_SIZE;
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localparam WAY_SIZE = $clog2(NUM_WAYS);
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typedef struct packed {
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logic[BYTE_OFFSET_SIZE - 1:0] byte_offset;
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logic[SET_SIZE - 1:0] set;
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logic[TAG_SIZE - 1:0] tag;
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} cache_addr;
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typedef enum logic[1:0] {
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READ = 'b00,
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WRITE_UNVALID = 'b10,
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REPLACE = 'b11
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} cache_state;
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cache_addr packed_addr;
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cache_state state;
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logic[WAY_SIZE - 1:0] valid_encode, next_unvalid_way;
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PriorityEncoder #(.N(WAY_SIZE)) valid_flags_encoder(valid_flags, valid_encode, valid_flags_encoder_valid);
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PriorityEncoder #(.N(WAY_SIZE)) read_way_encoder(hits, read_way, read_way_encoder_valid);
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logic valid;
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always_comb begin
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packed_addr = cache_addr'(addr);
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set = packed_addr.set;
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tag = packed_addr.tag;
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hit = |hits;
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valid = &valid_flags;
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state = cache_state'{write_enable, valid};
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case(state)
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READ: begin
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cru_enable = 0;
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if (read_way_encoder_valid)
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way = read_way;
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else
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way = 'd0;
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end
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WRITE_UNVALID: begin
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cru_enable = 0;
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way = next_unvalid_way;
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end
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REPLACE: begin
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cru_enable = 1;
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way = replace_way;
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end
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default: begin
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cru_enable = 0;
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way = 'dx;
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end
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endcase
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if (valid_flags_encoder_valid)
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next_unvalid_way = valid_encode + 'd1;
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else
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next_unvalid_way = 'd0;
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end
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/*
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always_ff @(posedge clk) begin
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end*/
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endmodule
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