78 lines
1.6 KiB
Systemverilog
78 lines
1.6 KiB
Systemverilog
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`timescale 1ns / 1ps
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module TwoWayLRUCache #(
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parameter ADDR_SIZE = 32,
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parameter NUM_SETS = 16,
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parameter BLOCK_SIZE = 32
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)(
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input logic clk, rst,
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input logic[ADDR_SIZE - 1:0] addr,
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input logic write_enable,
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input logic[BLOCK_SIZE - 1:0] write_data,
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output logic[BLOCK_SIZE - 1:0] read_data,
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output logic hit
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);
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localparam NUM_WAYS = 2;
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localparam NUM_BLOCK_BYTES = BLOCK_SIZE / 4;
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localparam BYTE_OFFSET_SIZE = $clog2(NUM_BLOCK_BYTES);
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localparam WAY_SIZE = $clog2(NUM_WAYS);
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localparam SET_SIZE = $clog2(NUM_SETS);
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localparam TAG_SIZE = ADDR_SIZE - SET_SIZE - BYTE_OFFSET_SIZE;
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logic[NUM_WAYS - 1:0] valid_flags;
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logic[NUM_WAYS - 1:0] hits;
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logic[WAY_SIZE - 1:0] way;
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logic[SET_SIZE - 1:0] set;
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logic[TAG_SIZE - 1:0] tag;
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CacheMemory #(
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ADDR_SIZE,
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NUM_SETS,
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NUM_WAYS,
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BLOCK_SIZE
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) cache_memory(
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clk,
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rst,
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way,
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set,
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tag,
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write_enable,
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write_data,
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read_data,
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hits,
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valid_flags
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);
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TwoWayLRUCRU #(
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ADDR_SIZE,
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NUM_SETS,
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BLOCK_SIZE
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) cache_replace_unit(
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clk,
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rst,
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addr,
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cru_enable,
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replace_preferred_way
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);
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CacheController #(
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ADDR_SIZE,
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NUM_SETS,
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NUM_WAYS,
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BLOCK_SIZE
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) cache_controller (
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clk,
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addr,
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write_enable,
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replace_preferred_way,
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hits,
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valid_flags,
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set,
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tag,
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way,
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hit,
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cru_enable
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);
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endmodule
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