22 lines
349 B
Systemverilog
22 lines
349 B
Systemverilog
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`timescale 1ns / 1ps
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module Test_InstrMemory();
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logic[31:0] addr;
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logic[31:0] instr;
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InstructionMemory instruction_memory(
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.addr(addr),
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.instr(instr)
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);
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initial begin
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addr='d1;
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#20
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addr='d11;
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#20
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addr='d12;
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#20
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addr='d13;
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end
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endmodule
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