RVSCC/rtl/rotate_cru.sv

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Systemverilog
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`include "timescale.sv"
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module rotate_cru#(
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parameter ADDR_SIZE = 32,
parameter NUM_SETS = 16,
parameter NUM_WAYS = 4,
parameter BLOCK_SIZE = 32
)(
input logic clk, rst,
input logic replace,
output logic[LRU_INDEX_SIZE - 1:0] preferred
);
logic[LRU_INDEX_SIZE - 1:0] write_preference;
always_comb begin
preferred = write_preference;
end
always_ff @(posedge clk) begin
if (rst)
write_preference <= 0;
else if(replace)
write_preference += 1;
end
endmodule