RVSCC/test/Test_CPU.sv

`timescale 1ns / 1ps
module Test_CPU();
    logic clk, reset;
    CPU cpu(clk, reset);
    always #10 clk = ~clk;
    initial begin
        clk = 0;
        reset = 1;
        #100
        reset = 0;
    end
endmodule
Add tests 2022-12-03 00:22:28 +00:00			`timescale 1ns / 1ps
			`module Test_CPU();`
			`logic clk, reset;`
Add cache 2023-01-01 22:28:56 +00:00			`CPU cpu(clk, reset);`
Update CPU 2022-12-20 05:19:32 +00:00			`always #10 clk = ~clk;`
Add tests 2022-12-03 00:22:28 +00:00			`initial begin`
Update CPU 2022-12-20 05:19:32 +00:00			`clk = 0;`
Add tests 2022-12-03 00:22:28 +00:00			`reset = 1;`
Fix tests 2022-12-24 01:14:04 +00:00			`#100`
Add tests 2022-12-03 00:22:28 +00:00			`reset = 0;`
			`end`
			`endmodule`